Edwin Carreño

prof_pic.jpg

Room 4/410

Im Neuenheimer Feld 205

69117, Heidelberg, Germany

Engineer with experience in ASIC design, computer architecture, and large-scale data processing. In industry, he has contributed to developing data pipelines, supporting infrastructure decisions, and applying machine learning techniques for applications such as fraud detection. His academic work includes the design and implementation of an integrated circuit for data compression in the ALICE experiment at CERN, completed with a silicon tapeout in 130nm technology at TSMC. During his master’s studies, he focused on software engineering and deep learning, particularly in computer vision and inference under uncertainty, with both his bachelor’s and master’s theses earning the maximum grade.

news

No news so far...

latest posts

selected publications

  1. IEEE
    integrated-circuit.gif
    A 3.9 compression-ratio Huffman encoding scheme for the large ion collider on 65nm and 130nm CMOS technologies
    In 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016